Datasheet

Chapter 1

Personal Computer System Components

time is essentially the difference between the time when the information is requested

from memory and the time when the data is returned. Common access times attributed

to asynchronous DRAM were in the 40- to 120-nanosecond (ns) vicinity. A lower access

time is obviously better for overall performance.

Because asynchronous DRAM is not synchronized to the frontside bus, you would

often have to insert wait states through the BIOS setup for a faster CPU to be able to use

such memory. These wait states represented intervals that the CPU had to mark time and

do nothing while waiting for the memory subsystem to become ready again for subse-

quent access.

Common asynchronous DRAM technologies included Fast Page Mode (FPM), Extended

Data Out (EDO), and Burst EDO (BEDO). Feel free to investigate the details of these par-

ticular technologies, but a thorough discussion of these memory types is not necessary here.

The A+ technician should be concerned with synchronous forms of RAM, which are the

only types of memory being installed in mainstream computer systems today.

Synchronous DRAM

Synchronous DRAM (SDRAM) shares a common clock signal with the computer’s sys-

tem-bus clock, which provides the common signal that all local-bus components use for

each step that they perform. This characteristic ties SDRAM to the speed of the FSB and,

hence, the processor, eliminating the need to conﬁgure the CPU to wait for the memory

to catch up.

Originally, SDRAM was the term used to refer to the only form of synchronous DRAM

on the market. As the technology progressed, and more was being done with each clock

signal on the FSB, various forms of SDRAM were developed. What was once called sim-

ply SDRAM needed a new name retroactively. Today, we use the term single data rate

SDRAM (SDR SDRAM) to refer to this original type of SDRAM.

SDR SDRAM

With SDR SDRAM, every time the system clock ticks, one bit of data can be transmitted

per data pin, limiting the bit rate per pin of SDRAM to the corresponding numerical value

of the clock’s frequency. With today’s processors interfacing with memory using a parallel

data-bus width of 8 bytes (hence the term 64-bit processor), a 100MHz clock signal pro-

duces 800MBps. That’s megabytes per second, not megabits. Such memory modules are

referred to as PC100, named for the true FSB clock rate they rely on. PC100 was preceded

by PC66 and succeeded by PC133, which used a 133MHz clock to produce 1067MBps of

throughput.

Note that throughput in megabytes per second is easily computed as eight times the rat-

ing in the name. This trick works for the more advanced forms of SDRAM as well. The

common thread is the 8-byte system data bus. Incidentally, you can double throughput

results when implementing dual-channel memory.

DDR SDRAM

Double data rate (DDR) SDRAM earns its name by doubling the transfer rate of ordinary

SDRAM by double-pumping the data, which means transferring it on both the rising and

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