Datasheet
40
Chapter 1
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Personal Computer System Components
a memory bank. A bank of memory is required for the computer system to electrically
recognize that memory or additional memory has been installed. The width of the system
data bus, the external bus of the processor, dictates how many memory chips or modules
are required to satisfy a bank. For example, one 32-bit, 72-pin SIMM satisfies a bank for
a 32-bit CPU, such as a 386 or 486 processor. Two such modules are required to satisfy a
bank for a 64-bit processor, a Pentium, for instance. However, only a single 64-bit, 168-
pin DIMM is required to satisfy the same Pentium processor. For those modules that have
fewer than eight or nine chips mounted on them, more than one bit for every byte is being
handled by some of the chips. For example, if you see three chips mounted, the two larger
chips probably handle 4 bits, a nybble, from each byte stored, and the third, smaller chip
probably handles the single parity bit for each byte.
Even and odd parity schemes operate on each byte in the set of memory chips. In each
case, the number of bits set to a value of 1 is counted up. If there are an even number of 1-bits
in the byte (0, 2, 4, 6, or 8), even parity stores a 0 in the ninth bit, the parity bit; otherwise,
it stores a 1 to even up the count. Odd parity does just the opposite, storing a 1 in the parity
bit to make an even number of 1s odd and a 0 to keep an odd number of 1s odd. You can see
that this is effective only for determining if there was a blatant error in the set of bits received,
but there is no indication as to where the error is and how to fix it. Furthermore, the total
1-bit count is not important, only whether it’s even or odd. Therefore, in either the even or
odd scheme, if an even number of bits is altered in the same byte during transmission, the
error goes undetected because flipping 2, 4, 6, or all 8 bits results in an even number of 1s
remaining even and an odd number of 1s remaining odd.
Mark and space parity are used in systems that want to see 9 bits for every byte trans-
mitted but don’t compute the parity bit’s value based on the bits in the byte. Mark parity
always uses a 1 in the parity bit, and space parity always uses a 0. These schemes offer less
error detection capability than the even and odd schemes because only changes in the parity
bit can be detected. Again, parity checking is not error correction; it’s error detection only,
and not the best form of error detection at that. Nevertheless, finding an error can lock up
the entire system and display a memory parity error. Enough of these errors and you need to
replace the memory.
In the early days of personal computing, almost all memory was parity-based. Compaq
was one of the first manufacturers to employ non-parity RAM in their mainstream systems.
As quality has increased over the years, parity checking in the RAM subsystem has become
rarer. As noted earlier, if parity checking is not supported, there will generally be fewer
chips per module, usually one less per column of RAM.
Error Checking and Correction
The next step in the evolution of memory error detection is known as error checking and cor-
recting (ECC). If memory supports ECC, check bits are generated and stored with the data.
An algorithm is performed on the data and its check bits whenever the memory is accessed. If
the result of the algorithm is all zeros, then the data is deemed valid and processing continues.
ECC can detect single- and double-bit errors and actually correct single-bit errors.
In this section, we’ll outline the major types of computer memory as well as the methods
of implementing, or packaging, such memory.
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