User manual
Wide Bank 28 DS3 - Release 2.4 July 2004 2-29
Product Description
Tests and Loopbacks
Tests and Loopbacks
Transmission Path Verification ... 2-29
Low-Speed Loopback Modes ... 2-30
C-bit FEAC Loopback Code Word Detection ... 2-31
NIU Loopcode Detection ... 2-31
Low-Speed Performance Monitoring ... 2-32
DS3 Loopback Modes ... 2-32
DS3 Loopcode Detection ... 2-34
Internal Tests ... 2-34
DS3 Alarm and Performance Monitoring ... 2-34
Transmission Path Verification
Verification of transmission data paths is a unique self-diagnostic capability of the Wide Bank 28
DS3. The low-speed transceivers include a pseudo-random bit sequence (PRBS unframed 2
15
-1 as
defined by ITU -T O.151) generator, detector, and bit error counter. Because these have the
flexibility of being placed in either the receive or transmit low-speed stream, several Bit Error Rate
test modes are available, in conjunction with the DS3 Framer. Individual DS1 or E1 bit error rate
testing may be conducted toward the low-speed equipment (the “drop”), in the DS3 line, or
internally to the Wide Bank (part of self-test). Following activation of the PRBS pattern generation,
received pattern synchronization is displayed along with bit error rate counts for the low-speed
circuits under test.