User manual

Product Description
Overview
2-4 July 2004 Wide Bank 28 DS3 - Release 2.4
Redundant Architecture
The Wide Bank 28 DS3 multiplexer uses two DS3 processors, which handle the DS3 interfaces, and
a backplane bus that accesses the low-speed interfaces. It also contains up to seven active low-speed
circuit boards and one optional spare circuit board that connect to the low-speed interfaces.
Figure 2-1 Functional Block Diagram
Framer
Microprocessor
High-Speed
Controller
Card A
4xDS1
or
3xE1
D C B A
Primary
DS3
(Working)
Secondary
DS3
(Protection)
Spare
Card
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Card
Position
1
2
3
4
5
6
7
Circuit
Number
Protection Group
4xDS1
or
3xE1
4xDS1
or
3xE1
4xDS1
or
3xE1
4xDS1
or
3xE1
4xDS1
or
3xE1
4xDS1
or
3xE1
Spare
Note: DS1 and E1 cards cannot be mixed.
E1 circuits use Protection Groups A, B, and C.
High-Speed
Controller
Card B
Trans-
ceiver
Framer
Microprocessor
Trans-
ceiver