Datasheet

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PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 95 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.5.8.3 ILR register
The Interrupt Level Register is used to program the level of the external interrupts.
Firmware can write to this register at any time.
Table 137. PCR ILR register (address 6202h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol - porpulse_
latched
- enable_pdselif - gpirq_level int1_level int0_level
Reset 010 0 0 0 0 0
Access R R/W R R/W R R/W R/W R/W
Table 138. Description of PCR ILR bits
Bit Symbol Description
7- Reserved
6 porpulse_latched Indicates that a reset has been generated. When set to logic 1,
indicates that the system has been reset. The firmware can write a “0”
during the firmware reset sequence.
5- Reserved
4 enable_pdselif Indicates that a reset has been generated. When set to logic 1,
P33_INT1 directly controls state of host interface pins:
If P33_INT1 is set to logic 1, host interface output pins are driven
according to selected interface protocol
If P33_INT1 is set to logic 0, host interface output pins are set into
high-impedance state
When set to logic 0, P33_INT1 does not control host interface pins. Their
state is determined by selected interface protocol.
enable_pdselif P33_INT1 State of host interface pins
0xActive
1 0 High Impedance
11Active
3 - Reserved.
2 gpirq_level Selects gpirq interrupt level. When set to logic 1, wake-up condition is
true when gpirq is high.
When set to logic 0, wake-up condition is true when gpirq is low.
1 int1_level Selects P33_INT1 interrupt level. When set to logic 1, wake-up condition
is true when P33_INT1 is low.
When set to logic 0, wake-up condition is true when P33_INT1 is high.
0 int0_level Selects P32_INT0 interrupt level. When set to logic 1, wake-up condition
is true when P32_INT0 is high.
When set to logic 0, wake-up condition is true when P32_INT0 is low.