Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 94 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.5.8 PCR register description
8.5.8.1 CFR register
The Clock Frequency Register is used to select the frequency of the CPU and its
associated peripherals. The clock frequency can be changed dynamically by writing to this
register at any time.
8.5.8.2 CER register
The Clock Enable Register is used to enable or disable the clock of the HSU (frequency is
fixed at 27.12 MHz). The clock can be switched on or off at any time.
Table 133. PCR CFR register- (address 6200h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol ------cpu_freq[1:0]
Reset 00000010
Access RRRRRRR/WR/W
Table 134. Description of PCR CFR bits
Bit Symbol Description
7 to 2 - Reserved
1 to 0 cpu_frq[1:0] Select CPU clock frequency.
cpu_frq[1:0] CPU clock frequency
00 27.12 MHz
01 13.56 MHz
10 6.78 MHz
11 27.12 MHz
Table 135. PCR CER register (address 6201h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol - - - - hsu_enable - - -
Reset 0000 1 110
Access RRRRR/WRRR
Table 136. Description of PCR CER bits
Bit Symbol Description
7 to 4 - Reserved.
3 hsu_enable Enable HSU clock. When 1, HSU is enabled. When 0, HSU is disabled.
2 to 0 - Reserved.