Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 93 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.5.6 Remote wake-up from SPD
The PN532 can be woken up from a Soft-Power-Down mode when an event occurs on
one of the wake up sources, which has been enabled. There are eight wake-up sources:
• P32_INT0
• P33_INT1
• RF field detected (RF_DETECT)
• HSU wake-up (HSU_ON)
• I
2
C wake-up (I
2
C_ON)
• SPI wake-up (SPI_ON)
• NFC_WI counters
• GPIRQ: P34, P35, P50_SCL, P71.
When one of these signals is asserted, if its corresponding enable bit is set (see Table 144
on page 97), the Power Sequencer starts the wake-up sequence. The wake up event can
only be serviced if the Power Sequencer is in the Stopped state, which means the PN532
is fully entered in Soft-Power-Down mode.
Figure 25
illustrates the wake-up mechanism, using an event on P33_INT1 as an
example. CPU_CLK is active T1 after the falling edge of P33_INT1 and the PN532 is
ready. T1 depends on the choice of crystal oscillator and its layout. For devices such as
TAS-3225A, TAS-7 or KSS2F, T1 is a maximum of 2ms. Exit from the Power-down mode
is signaled by CPU_PD going low one clock cycle later.
8.5.7 PCR extension registers
The PCR is controlled via several registers given in Table 132:
Fig 25. Remote wake-up from Power-down with P33 as wake-up source
CPU_CLK
P33_INT1
(if active low)
OSC27_CLK
CPU_PD
T1
Table 132. PCR registers
Name Size [bytes] Address offset Description Reset R/W
CFR 1 6200h Clock Frequency Register 02 R/W
CER 1 6201h Clock Enable Register 0E R/W
ILR 1 6202h Interrupt Level Register 40 R/W
Control 1 6203h Control C0 R/W
Status 1 6204h Status 00 R
Wakeupen 1 6205h Wake-up Enable 00 R/W