Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 91 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.5.2 27.12 MHz crystal oscillator
The 27.12 MHz clock applied to the PN532 is the time reference for the embedded
microcontroller. Therefore stability of the clock frequency is an important factor for reliable
operation. It is recommended to adopt the circuit shown in Figure 24
.
8.5.3 Reset modes
The possible reset mechanisms are listed below:
• Supply rail variation
When DVDD falls below 2.4 V , the POR (Power-On-Reset) asserts an internal reset
signal. The Power Sequencer disables all clocks. When DVDD rises above 2.4V, the
POR deasserts the internal reset signal and the Power Sequencer starts the power-up
sequence. Once the PN532 is out of reset, the RSTOUT_N pin is driven high.
• Glitch on DVDD
When DVDD falls below 2.35 V for more than 1 ms, the POR asserts an internal reset
signal. The power sequencer starts the Power-down sequence. The PN532 goes into
reset and the RSTOUT_N signal is driven low.
• Hard Power Down mode (HPD)
When RSTPD_N is set to logic 0, the PN532 goes into Hard Power Down (HPD)
mode. The PN532 goes into reset and the RSTOUT_N signal is driven low. The power
consumption is at the minimum. DVDD is tied to ground and ports are disconnected
from their supply rails.
When in Hard Power Down mode, the GPIO pins are forced in quasi bidirectional
mode. Referring to Figure 7 on page 41
, en_n = e_pu = “1”, e_p = “0”. e_hd = “1” if
GPIO pin value is “1” and e_hd = “0” if GPIO pin value is “0”.
Fig 24. 27.12 MHz crystal oscillator connection
CC
Crystal
OSCIN
OSCOUT
PN532
27.12 MHz