Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 88 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.4.1.5 LDO register
Table 126. LDO register- (address 6109h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol - - overcurrent_
status
sel_overcurrent[1:0]
-
enoffset soft_
highspeedreg
control_
highspeedreg
Reset 00 0 0 0 1 0 0
Access R R R R/W R/W R/W R/W R/W
Table 127. Description of LDO bits
Bit Symbol Description
7 to 6 - Reserved
5 overcurrent_status Set to logic 1 by PN532 when overcurrent is detected.
The bit IE1_0 of register IE1 (see Table 13 on page 18
) has also to
be set to logic 1 to enable the corresponding CPU interrupt.
4 to 3 sel_overcurrent[1:0] Select overcurrent threshold.
00: 300 mA
01: 210 mA
10: 180 mA
11: 150 mA
2 enoffset Enable of the LDO offset. When set to logic 1, offset is present.
1 soft_highspeedreg Control the LDO regulation speed. When set to logic 0, the
bandwidth of LDO is reduced to filter bursts on VBAT.
When set to logic 1, the bandwidth is increased to establish DVDD
supply quickly.
0 control_highspeedreg Select the control source of the LDO regulation speed. When
set to logic 1, LDO bandwidth controlled by soft_highspeedreg.
When set to logic 0, LDO bandwidth controlled by output of RF
level detector. When RF is detected, bandwidth is reduced.