Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 83 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.3.5.7 SPIstatus register
The SPIstatus register is byte addressable. It contains bits which are used to monitor the
status of the SPI interface, including normal functions, and exception conditions. The
primary purpose of this register is to detect completion of a data transfer. The remaining
bits in this register are exception condition indicators.
Table 124. SPIstatus register (SFR: address AAh) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol ----TR_FERCV_OVR-READY
Reset00000 0 0 0
Access RRRRR/WR/WR/WR/W
Table 125. Description of SPIstatus bits
Bit Symbol Description
7 to 4 - Reserved.
3TR_FETransmit FIFO Empty: Set to logic 1 when the host attempts to read a new
byte and FIFO manager is empty. An interrupt can be generated if enabled
(see IE1 bit in register SPIcontrol).
It is set to logic 0 by firmware.
2 RCV_OVR Receive Overrun: Set to logic 1 when the host attempts to write a new byte
and FIFO manager is full, or has not yet processed the previous byte. An
interrupt can be generated if enabled (see IE0 bit in register SPIcontrol)
It is set to logic 0 by firmware.
1- Reserved. This bit must be set to logic 0.
0 READY Ready flag. The firmware set READY to logic 1 to inform the host when
PN532 is ready to send data.