Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 81 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.3.5.5 FIFO manager write access
MISO is maintained at logic 0. Once a byte is received, a write request is sent to the FIFO
manager and the byte is loaded from SPI shift register into Receive FIFO of the FIFO
manager.
8.3.5.6 SPIcontrol register
SPIcontrol register contains programmable bits used to control the function of the SPI
block. This register has to be set prior to any data transfer.
Fig 17. SPI FIFO manager write access
FIFO manager write access
NSS
DATA
Write
MOSI
MISO
DATA
DATA
DATA
00000000
00000000
00000000
N/A
DATA
00000000
Table 122. SPIcontrol register (SFR: address A9h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol - - Enable - CPHA CPOL IE1 IE0
Reset00000000
Access R R R/W R R/W R/W R/W R/W
Table 123. Description of SPIcontrol bits
Bit Symbol Description
7 to 6 - Reserved.
5 Enable SPI enable: When set to logic 1, enables the SPI interface assuming that
selif[1:0] are set to 01b.
4 - Reserved.
3CPHAClock PHAse: This bit controls the relationship between the data and the
clock on SPI transfers.
When set to logic 0: Data is always sampled on the first clock edge of SCK.
When set to logic 1: Data is always sampled on the second clock edge of SCK.
2CPOLClock POLarity: This bit controls the polarity of SCK clock.
When set to logic 1, SCK starts from logic 0 else starts from logic 1.
1IE1 Interrupt Enable 1: When set to logic 1, the hardware interrupt generated by
TR_FE in SPIstatus register is enabled.
The bit IE1_5 of register IE1 (see Table 13 on page 18
) has also to be set to
logic 1 to enable the corresponding CPU interrupt.
0IE0 Interrupt Enable 0: When set to logic 1, the hardware interrupt generated by
RCV_OVR in SPIstatus register is enabled.
The bit IE1_5 of register IE1 (see Table 13 on page 18
) has also to be set to
logic 1 to enable the corresponding CPU interrupt.