Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 80 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.3.5.2 Protocol
Once the FIFO is full enough (see FIFO manager thresholds in Table 91 on page 67
), the
CPU sets bit READY in the SPI Status register to logic 1. Polling the SPI Status register,
the host is informed of the READY flag and can start the data transfer.
The protocol used is based on:
• ADDRESS / DATA protocol for status data exchanges
• ADDRESS / DATA / DATA / DATA... for data transfers
An exchange starts on the falling edge of NSS and follows the diagram described below.
8.3.5.3 SPI status register read
There is in that case no read request going to the FIFO manager.
The content of the status register is loaded in the SPI shift register.
8.3.5.4 FIFO manager read access
Bytes are loaded from the FIFO manager into the SPI shift register and sent back to the
host.
Remark: for proper operation, the firmware should write an additional byte in the FIFO
manager (FDATA). This byte will not be transmitted.
Fig 15. SPI Status register read access
SPI Status register read access:
STATUS
Read
NSS
MOSI
N/A
Status DATA
MISO
N/A
Fig 16. SPI FIFO manager read access
FIFO manager read access
NSS
DATA
Read
N/A
DATA
DATA
DATA
MOSI
MISO
N/A
DATA