Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 8 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
7.2 Pin description
Table 3. PN532 Pin description
Symbol Pin Type Ref
Voltage
Description
DVSS 1 PWR Digital ground.
LOADMOD 2 O DVDD Load modulation signal.
TVSS1 3 PWR Transmitter ground.
TX1 4 O TVDD Transmitter output 1: transmits modulated 13.56 MHz energy
carrier.
TVDD 5 PWR Transmitter power supply.
TX2 6 O TVDD Transmitter output 2: transmits modulated 13.56 MHz energy
carrier.
TVSS2 7 PWR Transmitter ground.
AVDD 8 PWR Analog power supply.
VMID 9 O AVDD Internally generated reference voltage to bias the receiving
path
RX 10 I AVDD Receiver input.
AVSS 11 PWR Analog ground.
AUX1 12 O AVDD Auxiliary output 1: analog and digital test signals.
AUX2 13 O AVDD Auxiliary output 2: analog and digital test signals.
OSCIN 14 I AVDD Crystal oscillator input: to oscillator inverting amplifier.
OSCOUT 15 O AVDD Crystal oscillator output: from oscillator inverting amplifier.
I0 16 I DVDD Host interface selector 0.
I1 17 I DVDD Host interface selector 1.
TESTEN 18 I DVDD Reserved for test: connect to ground for normal operation.
P35 19 IO DVDD General purpose IO.
N.C. 20 Not connected.
N.C. 21 Not connected.
N.C. 22 Not connected.
PVDD 23 PWR Pad power supply.
P30 /
UART_RX
24 IO PVDD General purpose IO / Debug UART receive input.
P70_IRQ 25 IO PVDD General purpose IO. Can be used as Interrupt request to host.
RSTOUT_N 26 O PVDD Reset indicator: when low, circuit is in reset state.
NSS /
P50_SCL /
HSU_RX
27 IO PVDD Host interface pin: SPI Not Slave Selected (NSS) or I
2
C clock
(SCL) or HSU receive (HSU_RX). Refer to Table 72 on
page 48 for details.
MOSI /
SDA /
HSU_TX
28 IO PVDD Host interface pin: SPI Master Out Slave In (MOSI) or I
2
C
data (SDA) or HSU transmit (HSU_TX). Refer to Table 72 on
page 48 for details.
MISO / P71 29 IO PVDD Host interface pin: SPI Master In Slave Out (MISO). Refer to
Table 72 on page 48
for details.
Can be used as general purpose IO.