Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 79 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.3.5 Serial Parallel Interface (SPI)
The SPI has the following features:
• Compliant with Motorola de-facto Serial Peripheral Interface (SPI) standard
• Synchronous, Serial, Half-Duplex communication, 5 MHz max
• Slave configuration
• 8 bits bus interface
Through the SPI interface, the host can either access the FIFO manager (acting as data
buffer) or the SPI status register. This selection is made through the hereafter described
protocol.
The SPI interface is managed by 2 SFRs.
8.3.5.1 Shift register pointer
A shift register is used to address the SPI interface. The value loaded in this register is
either the first byte of the FIFO manager or the SPI status register.
The first byte received from the host will contain the address of the register to access (SPI
status or FIFO manager FDATA) and also whether it is a SPI write or read. This character
is managed by hardware.
The bits used to define these operations are the 2 LSBs of the first byte.
Table 120. SPI SFR register list
Name Size
[bytes]
SFR
address
Description R/W
SPIcontrol 1 A9h SPI control bits R/W
SPIstatus 1 AAh SPI Status/Error bits R
Table 121. SPI operation
Bit 1 Bit 0 Operation
0 0 No effect
0 1 FIFO manager write access
1 0 SPI Status register read access
1 1 FIFO manager read access
Fig 14. Memory manager shift register management
SPI Status
SHIFT REGISTER
STATUS or DATA
FIFO manager
(Decoded output of First byte)
FDATA