Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 77 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.3.4.6 HSU_CTR register
This register controls the configuration of the HSU.
Table 113. HSU_CTR register (SFR: address ACh) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol hsu_wu_
en
start_frame tx_stopbit[1:0] rx_stopbit tx_en rx_en soft_reset_n
Reset 00000001
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 114. Description of HSU_CTR bits
Bit Symbol Description
7 hsu_wu_en HSU wake-up enable. When set to logic 1 this bit re-activates the NSS / SCL
/ HSU_RX rising-edge counter. When the counter is 5 then a signal hsu_on is
activated. This signal is one of the possible wake-up events from
Soft-Power-Down mode in the PCR block.
The firmware shall set this bit to logic 1 just before requesting a
Soft-Power-Down mode.
The bit HSU_on_en of register PCR Wakeupen (see Table 144 on page 97
)
has also to be set to logic 1 to enable the corresponding PN532 wake-up.
6 start_frame Enables the preamble filter for next frame. When set to logic 1 this bit
indicates that a new frame is coming. This re-activates the preamble filter
(when enabled), meaning that the first “00 00 FF” characters will not be sent
to the FIFO manager.
5:4 tx_stopbit[1:0] Defines the number of stop bit during transmission. These 2 bits define
the number of Stop bit(s) inserted at the end of the transmitted frame.
The number of Stop bit(s) transmitted is equal to tx_stopbit +1.
3 rx_stopbit Defines the number of stop bit during reception. This bit defines the
number of Stop bit(s) inserted at the end of the received frame.
The number of Stop bit(s) expected in reception is equal to rx_stopbit +1.
2tx_en Enables the transmission of HSU. When set to logic 1 this bit enables the
transmission of characters.
When set to logic 0, the transmission is disabled only after the completion of
the current transmission.
1rx_en Enables the reception of the HSU. When set to logic 1 this bit enables the
reception of characters.
When set to logic 0, the reception is disabled only after the completion of the
current reception.
0 soft_reset_n HSU Reset. When set to logic 0, this bit disables the clock of the HSU_RX
control, HSU_TX control and baud rate generator modules.