Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 76 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.3.4.4 HSU wake-up generator
The wake-up generator is a 3-bit counter which counts on every rising edge of the
HSU_RX pin. When the counter reaches 5, the hsu_on signal is set to logic 1 in order to
wake up the PN532. This block is useful in Soft-Power-Down mode. The firmware shall
reset this counter just before going in Soft-Power-Down by writing a logic 1 in the
hsu_wu_en bit into the HSU_CTR register.
8.3.4.5 HSU_STA register
The SFR HSU_STA is the status register of the HSU.
Table 111. HSU_STA register (SFR: address ABh) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol set_bit - - disable_
preamb
irq_rx_
over_en
irq_rx_fer
_ en
irq_rx_
over
irq_rx_fer
Reset 00000000
Access R/W R R R/W R/W R/W R/W R/W
Table 112. Description of HSU_STA bits
Bit Symbol Description
7 set_bit When set to logic 0 during write operation, the bits set to logic 1 in the
write command are written to logic 0 in the register.
When set to logic 1 during write operation, the bits set to logic 1 in the
write command are written to logic 1 in the register.
6 to 5 - Reserved
4 disable_preamb Preamble filter disable. When set to logic 1, this bit disables the
preamble filtering, it means that HSU_RX line transmit any received
bytes to the FIFO manager.
3 irq_rx_over_en FIFO overflow interrupt enable. When set to logic 1, this bit enables the
interrupt generation when the bit irq_rx_over is set to logic 1.
The bit IE1_5 of register IE1 (see Table 13 on page 18
) has also to be set
to logic 1 to enable the corresponding CPU interrupt.
2 irq_rx_fer_en Framing error interrupt enable. When set to logic 1, this bit enables the
interrupt generation when the bit irq_rx_fer is set to logic 1.
The bit IE1_5 of register IE1 (see Table 13 on page 18
) has also to be set
to logic 1 to enable the corresponding CPU interrupt.
1 irq_rx_over Receive FIFO overflow interrupt. Set to logic 1 when the FIFO
manager is full (rcv_ack is set to logic 0) and when HSU shift register is
ready to send another byte to the FIFO manager.
0 irq_rx_fer Framing error interrupt. Set to logic 1 when a framing error has been
detected. Framing error detection is based on Stop bit sampling.
When Stop bit is expected at logic 1 but is sampled at logic 0, this bit is
set to logic 1.