Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 71 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.3.3.8 FITEN register
The FITEN register enables or disables the interrupt requests to the CPU. It is also used
to reset the content of the Receive and Transmit FIFO.
Table 104. FITEN register (SFR: address A1h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol TFLUSH RFLUSH EN_
WCOL_
IRQ
EN_
TWLL_
IRQ
EN_
TFF_
IRQ
EN_
RWLH_
IRQ
EN_
ROVR_
IRQ
EN_
RFF_
IRQ
Reset 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 105. Description of FITEN bits
Bit Symbol Description
7 TFLUSH When set to logic level 1, the pointer of the Transmit FIFO is reset. This bit
and RFLUSH must not be set at the same time.
6 RFLUSH When set to logic level 1, the pointer of the Receive FIFO is reset. This bit
and TFLUSH must not be set at the same time but one after the other.
5EN_WCOL_IRQENable Write COLlision IRQ: When set to logic 1, the WCOL_IRQ is
enabled.
The bit IE1_5 of register IE1 (see Table 13 on page 18
) has also to be set
to logic 1 to enable the corresponding CPU interrupt.
4 EN_TWLL_IRQ ENable Transmit WaterlLevelLow IRQ: When set to logic 1, the
TWLL_IRQ is enabled.
The bit IE1_5 of register IE1 (see Table 13 on page 18
) has also to be set
to logic 1 to enable the corresponding CPU interrupt.
3 EN_TFF_IRQ ENable Transmit FIFO Full IRQ: When set to logic level 1, the TFF_IRQ is
enabled.
The bit IE1_5 of register IE1 (see Table 13 on page 18
) has also to be set
to logic 1 to enable the corresponding CPU interrupt.
2 EN_RWLH_IRQ ENable Receive WaterLevel High IRQ: When set to logic 1, the
RWLH_IRQ is enabled.
The bit IE1_5 of register IE1 (see Table 13 on page 18
) has also to be set
to logic 1 to enable the corresponding CPU interrupt.
1 EN_ROVR_IRQ ENable Read OVeRrun IRQ: When set to logic 1, the ROVR_IRQ is
enabled.
The bit IE1_5 of register IE1 (see Table 13 on page 18
) has also to be set
to logic 1 to enable the corresponding CPU interrupt.
0EN_RFF_IRQENable Receive FIFO Full IRQ: When set to logic 1, the RFF_IRQ is
enabled.
The bit IE1_5 of register IE1 (see Table 13 on page 18
) has also to be set
to logic 1 to enable the corresponding CPU interrupt.