Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 70 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.3.3.7 FIT register
The FIT register contains 6 read-write bits which are logically OR-ed to generate an
interrupt going to the CPU.
Table 102. FIT register (SFR: address 9Fh) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol Reset - WCOL_
IRQ
TWLL_
IRQ
TFF_
IRQ
RWLH_
IRQ
ROVR_
IRQ
RFF_
IRQ
Reset 00 0 0 0 0 0 0
Access W R R/W R/W R/W R/W R/W R/W
Table 103. Description of FIT bits
Bit Symbol Description
7 Reset Reset: Set to logic 1, Reset defines that the bits set to logic 1 in the write
command are set to logic 0 in the register.
6- Reserved
5 WCOL_IRQ Write COLlision IRQ: This bit is set to logic 1 when the transmitted part of the
FIFO is already full (TFF is set to logic 1) and a new character is written by the
CPU in the data register.
4 TWLL_IRQ Transmit WaterlLevelLow IRQ: This bit is set to logic 1 when the number of
bytes stored into the Transmit FIFO is equal or smaller than the threshold
TWaterlevel.
3TFF_IRQ Transmit FIFO Full IRQ: This is set to logic 1 if the transmitted part of the FIFO
is full.
2RWLH_IRQReceive WaterLevel High IRQ: This bit is set to logic 1 when the number of
bytes stored into the Receive FIFO is greater or equal to the threshold
RWaterlevel.
1 ROVR_IRQ Read OVeRrun IRQ: This bit indicates that a read overrun has occured.It
occurs when the receiver part of the FIFO is full and a new data transfer is
completed. Then the new received data is lost and ROVR_IRQ is set.
0RFF_IRQ Receive FIFO Full IRQ: This bit is set to logic 1 if the received part of the FIFO
is full.