Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 69 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.3.3.6 SFF register
The register bits are used to allow the CPU to monitor the status of the FIFO. The primary
purpose is to detect completion of data transfers.
Table 100. SFF register (SFR: address 9Eh) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol FIFO_EN - TWLL TFF TFE RWLH RFF RFE
Reset 0 0101001
Access R/WRRRRRRR
Table 101. Description of SFF bits
Bit Symbol Description
7 FIFO_EN Fifo Enable: Set to logic 1 this bit enables the FIFO manager clock
(CPU_CLK).
Set to logic 0 the clock remains low.
6 - Reserved.
5TWLL Transmit WaterlLevelLow: This bit is set to logic 1 when the number
of bytes stored into the Transmit FIFO is equal or smaller than the
threshold TWaterlevel.
4TFF Transmit FIFO Full: This is set to logic 1 if the transmit part of the
FIFO is full. It is set to logic 0 when a transfer is completed.
3TFE Transmit FIFO Empty: This bit indicates when the transmit part of the
FIFO is empty.
It is set to logic 0 when the CPU writes a character in the data register.
2RWLH Receive WaterLevel High: This bit is set to logic 1 when the number
of bytes stored into the Receive FIFO is greater or equal to the
threshold RWaterlevel.
1RFF Receive FIFO Full: This bit is set to logic 1 if the receive part of the
FIFO is full. It is set to logic 0 by reading the FDATA register.
0RFE Receive FIFO Empty: This bit indicates when the receive part of the
FIFO is empty.
Set to logic 1, when the Receive FIFO is empty.
Set to logic 0, when the Receive FIFO contains at least 1 byte.