Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 68 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.3.3.4 FIFOFS register
This register indicates the number of bytes that the CPU can still load into the FIFO until
the Transmit FIFO is full.
8.3.3.5 FIFOFF register
This register indicates the number of bytes already received and loaded into the Receive
FIFO.
Table 96. FIFOFS register (SFR: address 9Ch) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol TransmitFreespace[7:0]
Reset 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 97. Description of FIFOFS register bits
Bit Symbol Description
7 to 0 TransmitFreespace[7:0] Freespace into the FIFO
Table 98. FIFOFF register (SFR: address 9Dh) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol ReceiveFullness[7:0]
Reset 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 99. Description of FIFOFF bits
Bit Symbol Description
7 to 0 ReceiveFullness[7:0] Number of bytes received in the FIFO