Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 67 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.3.3.2 RWL register
This register defines the warning level of the Receive FIFO for the CPU. It implies a FIFO
buffer overflow.
8.3.3.3 TWL register
This register defines the warning level of the Transmit FIFO for the CPU. It implies a FIFO
buffer underflow.
Table 91. Fifo manager SFR register list
Name Size
[bytes]
SFR
Address
Description Access
RWL 1 9Ah FIFO Receive Waterlevel: Controls the threshold of the
FIFO in reception
R/W
TWL 1 9Bh FIFO Transmit Waterlevel: Controls the threshold of the
FIFO in transmission
R/W
FIFOFS 1 9Ch FIFO Transmit FreeSpace: Status of the number of
characters which can still be loaded in the FIFO
R/W
FIFOFF 1 9Dh FIFO Receive Fullness: Status of the number of
received characters in the FIFO
R/W
SFF 1 9Eh Global Status/Error messages R
FIT 1 9Fh Interrupt Source R/W
FITEN 1 A1h Interrupt Enable and Reset FIFO R
FDATA 1 A2h Data reception/transmission buffer R/W
FSIZE 1 A3h Control the size of the FIFO in Reception R/W
Table 92. RWL register (SFR: address 9Ah) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol RWaterlevel[7:0]
Reset 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 93. Description of RWL bits
Bit Symbol Description
7 to 0 RWaterlevel[7:0] Overflow threshold of the Receive FIFO to set a warning
Table 94. TWL register (SFR: address 9Bh) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol TWaterlevel[7:0]
Reset 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 95. Description of TWL bits
Bit Symbol Description
7 to 0 TWaterlevel[7:0] Underflow threshold of the Transmit FIFO to set a warning