Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 66 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.3.3 FIFO manager
This block is designed to manage a RAM as a FIFO in order to optimize the data
exchange between the CPU and the HOST.
8.3.3.1 FIFO manager functional description
The RAM used for the FIFO is shared between the SPI and HSU interfaces. Indeed,
these interfaces cannot be used simultaneously. The selection of the interface used is
done by firmware. The FIFO manager block is the common part between the SPI and
the HSU interfaces. It consists of a Data register, a Status register and also some
registers to define the characteristics of the FIFO. These registers are addressed by the
CPU as SFRs.
The RAM used as a FIFO is divided into two part: a receive part and a transmit part.
This block also manages the possible conflicts existing around the FIFO between the
CPU and the interfaces. Indeed, a request coming from the interface (TR_req or
RCV_req) can be simultaneous with a request to access to the data register coming
from the CPU.
9 SFR registers are needed to manage the FIFO manager.
Fig 12. FIFO manager block diagram
DATA
Irq
SPI_DATA
HSU_DATA
CPU
SPI
ADQ
Control
HIGH
UART
SPEED
FIFO
Manager
RAM
CONTROL