Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 65 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.3.2.10 I
2
CADR register
The CPU can read from and write to this 8-bit SFR. I
2
CADR is not affected by the I
2
C
interface hardware. The content of this register is irrelevant when the I
2
C interface is in a
Master mode. In the Slave modes, the seven most significant bits must be loaded with the
microcontroller’s own Slave address, and, if the least significant bit is set to logic 1, the
general call address (00h) is recognized; otherwise it is ignored.
8.3.2.11 I
2
C_wu_control register
The wake up block has to be enabled before the whole chip enters in Soft-Power-Down
mode. The choice of the wake-up conditions is made within the register I
2
C_wu_control.
Read and Write conditions can be set together.
Table 87. I
2
CADR register (SFR: address DBh) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol SA[6:0] GC
Reset 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 88. Description of I
2
CADR bits
Bit Symbol Description
7 to 1 SA[6:0] Slave address. These bits correspond to the 7-bit Slave address which
will be recognized on the incoming data stream from the I
2
C bus. When
the Slave address is detected and the interface is enabled, a serial
interrupt SI will be generated to the CPU.
0GC General call. When set to logic 1, will cause the I
2
C logic to watch for
the general call address to be transmitted on the I
2
C bus. If a general
call address is detected and this bit is set to logic 1, SI will be set to
logic 1.
Table 89. I
2
C_wu_control register (address 610Ah) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol -----i
2
c_wu_en_wr i
2
c_wu_en_rd i
2
c_wu_en
Reset 00000 0 0 0
Access RRRRR R/W R/W R/W
Table 90. Description of I
2
C_wu_control bits
Bit Symbol Description
7 to 3 - Reserved.
2i
2
c_wu_en_wr When set to logic 1, the wake-up is valid for write commands
1i
2
c_wu_en_rd When set to logic 1, the wake-up is valid for read commands
0i
2
c_wu_en When set to logic 1, enable the I
2
C wake-up conditions.
The bit i
2
c_wu_en of register PCR Wakeupen (see Table 144 on
page 97) has also to be set to logic 1 to enable the corresponding
PN532 wake-up.