Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 64 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.3.2.9 I
2
CDAT register
I
2
CDAT contains a byte of I
2
C data to be transmitted or a byte which has just been
received. The CPU can read from and write to this 8-bit SFR while it is not in the process
of shifting a byte. This occurs when the I
2
C interface is in a defined state and the serial
interrupt flag SI is set to logic 1. Data in I
2
CDAT remains stable as long as SI is set to logic
1. The first bit to be transmitted is the MSB (bit 7), and, after a byte has been received, the
first bit of received data is located at the MSB of I
2
CDAT. While data is being shifted out,
data on the bus is simultaneously being shifted in; I
2
CDAT always contains the last data
byte present on the bus. Thus, in the event of lost arbitration, the transition from Master
Transmitter to Slave Receiver is made with the correct data in I
2
CDAT.
I
2
CDAT[7:0] and the ACK flag form a 9-bit shift register which shifts in or shifts out an 8-bit
byte, followed by an acknowledge bit. The ACK flag is controlled by the I
2
C interface
hardware and cannot be accessed by the CPU. I
2
C data are shifted through the ACK flag
into I
2
CDAT on the rising edges of clock pulses on P50_SCL. When a byte has been
shifted into I
2
CDAT, the I
2
C data are available in I
2
CDAT, and the acknowledge bit is
returned by the control logic during the ninth clock pulse. I
2
C data are shifted out from
I
2
CDAT via a buffer on the falling edges of clock pulses on P50_SCL.
When the CPU writes to I
2
CDAT, the buffer is loaded with the contents of I
2
CDAT[7] which
is the first bit to be transmitted to the SDA line. After nine serial clock pulses, the eight bits
in I
2
CDAT will have been transmitted to the SDA line, and the acknowledge bit will be
present in ACK. Note that the eight transmitted bits are shifted back into I
2
CDAT.
Table 85. I
2
CDAT register (SFR: address DAh) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol I
2
CDAT[7:0]
Reset 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 86. Description of I
2
CDAT bits
Bit Symbol Description
7 to 0 I
2
CDAT[7:0] I2C data. Eight bits to be transmitted or just received. A logic 1 in
I
2
CDAT corresponds to a logic 1 on the I
2
C bus, and a logic 0
corresponds to a logic 0 on the bus. I
2
C data shift through I
2
CDAT
from right to left.