Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 57 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.3.2.8 I
2
CSTA register
I
2
CSTA is an 8-bit read-only special function register. The three least significant bits are
always at logic 0. The five most significant bits contain the status code. There are 26
possible status codes. When I
2
CSTA contains F8h, no relevant state information is
available and no serial interrupt is requested. Reset initializes I
2
CSTA to F8h. All other
I
2
CSTA values correspond to defined I
2
C interface states. When each of these states is
entered, a serial interrupt is requested (SI = ‘1’), this can happen in any CPU cycle, and a
valid status code will be present in I
2
CSTA. This status code will remain present in I
2
CSTA
until SI is set to logic 0 by firmware.
Note that I
2
CSTA changes one CPU_CLK clock cycle after SI changes, so the new status
can be visible in the same machine cycle SI changes or possibly (in one out of six CPU
states) the machine cycle after that. This should not be a problem since you should not
read I
2
CSTA before either polling SI or entry of the interrupt handler (which in itself takes
several machine cycles).
Table 78. I
2
CSTA register (SFR: address D9h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol ST[7:0]
Reset 11111000
Access RRRRRRRR
Table 79. Description of I
2
CSTA bits
Bit Symbol Description
7 to 0 ST[7:0] Encoded status bit for the different functional mode. Several Status
codes are returned in a certain mode (Master Transmitter, Master
Receiver, Slave Transmitter, Slave Receiver) plus some miscellaneous
status codes that can be returned at any time.
Fig 11. I
2
C state machine of status behavior
IDLE
SI=1 => ST[7:0] = status
SI=0 => ST[7:0] = F8
INTERRUPT/
STATUS
AVA I L A B L E
SI=1
SI=0 =>ST[7:0] = F8