Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 55 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
4STOSTOP control. When the STO bit is set to logic 1, while the I
2
C interface is in
Master mode, a STOP condition is transmitted to the I
2
C bus. When the STOP
condition is detected on the bus, the I
2
C interface hardware automatically sets
STO to logic 0.
In Slave mode, STO may be set to logic 1 to recover from an error condition. In
this case, no STOP condition is transmitted to the I
2
C bus. However, the I
2
C
interface hardware behaves as if a STOP condition has been received and
switches to the defined “not addressed” Slave Receiver mode.
If the STA and STO bits are both set to logic 1, the STOP condition is transmitted
to the I
2
C bus if the I
2
C interface is in Master mode (in Slave mode, the I
2
C
interface generates an internal STOP condition which is not transmitted). The I
2
C
interface then transmits a START condition.
When the STO bit is set to logic 0, no STOP condition will be generated.
3SI Serial interrupt flag. When SI is set to logic 1, then if the serial interrupt from the
I
2
C interface port is enabled, the CPU will receive an interrupt. SI is set by
hardware when any one of 25 of the possible 26 states of the I
2
C interface are
entered. The only state that does not cause SI to be set to logic 1 is state F8h,
which indicates that no relevant state information is available.
While SI is set by hardware to logic 1, P50_SCL is held in logic 0 when the SCL
line is logic 0, and P50_SCL is held in high impedance when the SCL line is
logic 1.
SI must be set to logic 0 by firmware.
When the SI flag is set to logic 0, no serial interrupt is requested, and there is no
stretching of the SCL line via P50_SCL.
The bit IE1_4 of register IE1 (see Table 13 on page 18
) has also to be set to
logic 1 to enable the corresponding I
2
C interrupt to the CPU.
2AA Assert Acknowledge flag. If AA is set to logic 1, an acknowledge (low level to
SDA) will be returned during the acknowledge clock pulse on the P50_SCL line
when:
• The “own Slave address” has been received.
• The general call address has been received while the general call bit (GC) in
I
2
CADR is set.
• A data byte has been received while the I
2
C interface is in Master Receiver
mode.
• A data byte has been received while the I
2
C interface is in the addressed
Slave Receiver mode.
When the I
2
C interface is in the addressed Slave Transmitter mode, state C8h
will be entered after the last serial bit is transmitted. When SI is set to logic 0, the
I
2
C interface leaves state C8h, enters the Not-addressed Slave Receiver mode,
and the SDA line remains at logic 1. In state C8h, AA can be set to logic 1 again
for future address recognition.
When the I
2
C interface is in the Not-addressed Slave mode, its own Slave
address and the general call address are ignored. Consequently, no
acknowledge is returned, and a serial interrupt is not requested. Thus, the I
2
C
interface can be temporarily released from the I
2
C bus while the bus status is
monitored. While the I
2
C interface is released from the bus, START and STOP
conditions are detected, and I
2
C data are shifted in. Address recognition can be
resumed at any time by setting AA to logic 1.
If AA is set to logic 1 when the I
2
C own Slave address or the general call address
has been partly received, the address will be recognized at the end of the byte
transmission.
Table 77. Description of I
2
CCON bits …continued
Bit Symbol Description