Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 54 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.3.2.7 I
2
CCON register
The CPU can read from and write to this 8-bit SFR. Two bits are affected by the Serial IO
(the I
2
C interface) hardware: the SI bit is set to logic 1 when a serial interrupt is requested,
and the STO bit is set to logic 0 when a STOP condition is present on the I
2
C bus. The
STO bit is also set to logic 0 when ENS1 = ‘0’.
Table 76. I
2
CCON register (SFR: address D8h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol CR[2] ENS1 STA STO SI AA CR[1:0]
Reset 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 77. Description of I
2
CCON bits
Bit Symbol Description
7 CR[2] Serial clock frequency selection in Master mode. Together with CR[1:0], this
bit determines the clock rate (serial clock frequency) when the I
2
C interface is in
a Master mode. Special attention has to be made on the I
2
C bit frequency in case
of dynamic switching of the CPU clock frequency.
6ENS1Serial IO enable. When ENS1 bit is to logic 0, SDA and P50_SCL are in high
impedance. The state of SDA and P50_SCL is ignored, the I
2
C interface is in the
“not addressed” Slave state, and the STO bit in I
2
CCON is forced to logic 0. No
other bits are affected.
When ENS1 is logic 1, the I
2
C interface is enabled, assuming selif[1:0] bits are
10b (see Table 72 on page 48
).
ENS1 should not be used to temporarily release the I
2
C interface from the I
2
C
bus since, when ENS1 is set to logic 0, the I
2
C bus status is lost. The AA flag
should be used instead.
5STASTART control. When the STA bit is set to logic 1 to enter Master mode, the I
2
C
interface hardware checks the status of the I
2
C bus and generates a START
condition if the bus is free. If the bus is not free, then the I
2
C interface waits for a
STOP condition (which will free the bus) and generates a START condition after
a delay of a half clock period of the internal serial clock generator.
If STA is set to logic 1, while the I
2
C interface is already in a Master mode and
one or more bytes are transmitted or received, the I
2
C interface transmits a
repeated START condition.
STA may be set to logic 1 at any time. This includes the case when the I
2
C
interface is the addressed Slave.
When the STA bit is set to logic 0, no START condition or repeated START
condition will be generated.