Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 52 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
The first byte transmitted contains the Slave address of the transmitting device (7-bit SLA)
and the data direction bit. In this case the data direction bit (R/W) will be logic 1 (R). I
2
C
data are received via SDA while P50_SCL outputs the serial clock. I
2
C data are received
8 bits at a time. After each byte is received, an acknowledge bit is transmitted. START and
STOP conditions are output to indicate the beginning and end of a serial transfer.
In the Master receiver mode, a number of data bytes are received from a Slave
transmitter. The transfer is initialized as in the Master transmitter mode. When the START
condition has been transmitted, the interrupt service routine must load I
2
CDAT with the
7-bit Slave address and the data direction bit (SLA+R). The SI bit in I
2
CCON must then be
set to logic 0 before the serial transfer can continue.
When the Slave address and the data direction bit have been transmitted and an
acknowledgment bit has been received, the serial interrupt flag (SI) is set to logic 1 again,
and a number of status codes are possible in I
2
CSTA. The appropriate action to be taken
for each of the status codes is detailed in Table 81 on page 59
. After a repeated start
condition (state 10h), the I
2
C interface may switch to the Master transmitter mode by
loading I
2
CDAT with SLA+W.
8.3.2.4 Slave receiver mode
I
2
C data and the serial clock are received through SDA and P50_SCL. After each byte is
received, an acknowledge bit is transmitted. START and STOP conditions are recognized
as the beginning and end of a serial transfer. Address recognition is performed by
hardware after reception of the Slave address and direction bit.
In the Slave receiver mode, a number of data bytes are received from a Master
transmitter. To initiate the Slave receiver mode, I
2
CADR must be loaded with the 7-bit
Slave address to which the I
2
C interface will respond when addressed by a Master. Also
the least significant bit of I
2
CADR should be set to logic 1 if the interface should respond
to the general call address (00h). The control register, I
2
CCON, should be initialized with
ENS1 and AA set to logic 1 and STA, STO, and SI set to logic 0 in order to enter the Slave
receiver mode. Setting the AA bit will enable the logic to acknowledge its own Slave
address or the general call address and ENS1 will enable the interface.
When I
2
CADR and I
2
CCON have been initialized, the I
2
C interface waits until it is
addressed by its own Slave address followed by the data direction bit which must be ‘0’
(W) for the I
2
C interface to operate in the Slave receiver mode. After its own Slave
address and the W bit have been received, the serial interrupt flag (SI) is set to logic 1 and
a valid status code can be read from I
2
CDAT. This status code should be used to vector to
an interrupt service routine, and the appropriate action to be taken for each of the status
codes is detailed in Table 82 on page 60
. The Slave receiver mode may also be entered if
arbitration is lost while the I
2
C interface is in the Master mode.
If the AA bit is set to logic 0 during a transfer, the I
2
C interface will return a not
acknowledge (logic 1) to SDA after the next received data byte. While AA is set to logic 0,
the I
2
C interface does not respond to its own Slave address or a general call address.
However, the I
2
C bus is still monitored and address recognition may be resumed at any
time by setting AA. This means that the AA bit may be used to temporarily isolate the I
2
C
interface from the I
2
C bus.