Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 50 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.3.2 I
2
C interface
It is recommended to refer the I
2
C standard for more information.
The I
2
C interface implements a Master/Slave I
2
C bus interface with integrated shift
register, shift timing generation and Slave address recognition. I
2
C Standard mode (100
kHz SCLK) and Fast mode (400 kHz SCLK) are supported.
General Call +W is supported, not hardware General Call (GC +R).
The mains characteristics of the I
2
C module are:
• Support Master/Slave I
2
C bus
• Standard and Fast mode supported
• Wake-up of the PN532 on its own address
• Wake-up on General Call +W (GC +W)
The I
2
C module is control through 5 registers:
8.3.2.1 I
2
C functional description
The I
2
C interface may operate in any of the following four modes:
• Master Transmitter
• Master Receiver
• Slave Receiver
• Slave Transmitter
Two types of data transfers are possible on the I
2
C bus:
• Data transfer from a Master transmitter to a Slave receiver. The first byte transmitted
by the Master is the Slave address. Next follows a number of data bytes. The Slave
returns an acknowledge bit after each received byte.
• Data transfer from a Slave transmitter to a Master receiver. The first byte (the Slave
address) is transmitted by the Master. The Slave then returns an acknowledge bit.
Next follows the data bytes transmitted by the Slave to the Master. The Master returns
an acknowledge bit after each received byte except the last byte. At the end of the last
received byte, a “not acknowledge” is returned.
In a given application, the I
2
C interface may operate as a Master or as a Slave.
In the PN532, the I
2
C is typically configured as a Slave, because the host is Master.
Table 75. I
2
C register list
Name Size
[bytes]
Address Description Access
I
2
CCON 1 D8h (SFR) Control register R/W
I
2
CSTA 1 D9h (SFR) Status register R/W
I
2
CDAT 1 DAh (SFR) Data register R/W
I
2
CADR 1 DBh (SFR) Slave Address register R/W
i
2
c_wu_control 1 610Ah Control register for the I
2
C wake-up conditions R/W