Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 49 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.3.1.1 MIF register
The Config I0_I1 register is used to select the host interface. It manages also the polarity
of P33_INT1.
8.3.1.2 Configuration modes of the host interface pins.
In I
2
C mode, P50_SCL and SDA are configured in Open Drain mode.
In HSU mode, HSU_RX is in input mode and HSU_TX is in push-pull mode.
In SPI mode, NSS, MOSI and SCK are in inputs mode. MISO is in push-pull mode.
Table 73. Config I0_I1 register (address 6103h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol int1_pol - pad_I1 - pad_I0 enselif Selif[1:0]
Reset 00X0X 000
Access R/W R R/W R R/W R/W R/W R/W
Table 74. Description of Config I0_I1 bits
Bit Symbol Description
7 int1_pol When set to logic 1, the value of the P33_INT1 pin is inverted.
6 - Reserved.
5 pad_I1 When read this bit gives the state of the I1 pin.
4 - Reserved.
3 pad_I0 When read this bit gives the state of the I0 pin.
2 enselif When set to logic 1, this bit indicates that the selif bits are valid and that the
selected interface on the MIF can drive the pins.
The firmware must copy the value of the pads I0 and I1 to respectively selif[0]
and selif[1]
When set to logic 0, the MIF cannot drive the IO lines.
1:0 Selif[1:0] These bits are used by the firmware to select the host interface communication
link, see Table 72 on page 48
.