Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 48 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.3 Host interfaces
PN532 must be able to support different kind of interfaces to communicate with the HOST.
All the interfaces that have to be supported are exclusive.
• SPI interface
• I
2
C interface: Standard and Fast modes
• High Speed UART (HSU): supporting specific high baud rates
8.3.1 Multi-InterFace (MIF) description
The Multi-InterFace (MIF) manages the configuration of the host interface pins, supplied
by PVDD, according to the selected links with the bits selif[1:0] of register Config_I0_I1
(see Table 74 on page 49
):
The firmware must copy the value of the pads I0 and I1 to respectively selif[0] and selif[1].
Fig 10. Host interface block diagram
I
2
C
CPU
HOST
M
I
F
selif(1:0)
FIFO
Manager
SPI
HSU
RAM
PN532
Host Interfaces
Table 72. HOST interface selection
Selif [1:0] 00 01 10 11
Host interface selected HSU SPI I
2
C Reserved
Pin number
27 HSU_RX NSS P50_SCL -
28 HSU_TX MOSI SDA -
29 P71 MISO P71 -
30 P72 SCK P72 -