Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 46 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.2.2.5 P3CFGB register
[1] When CPU_PD is set to logic 1(see Table 7 on page 16), for P32_INT0 and referring to Section 8.2.1, e_hd
is forced to logic 1.
Remark: When in Hard power down mode, the P35 to P30 pins are forced in quasi
bidirectional mode. Referring to Figure 7
, en_n = e_pu = “1”, e_p = “0”. And e_hd = “1” if
P3x pin value is “1” and e_hd = “0” if P3x pin value is “0”.
Table 68. P3CFGB register (SFR: address FDh) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol --P3CFGB[
5]
P3CFGB[
4]
P3CFGB[
3]
P3CFGB[
2]
P3CFGB[
1]
P3CFGB[
0]
Reset 00000000
Access R R R/W R/W R/W R/W R/W R/W
Table 69. Description of P3CFGB bits
Bit Symbol Description
7 to 6 Reserved.
5 P3CFGB[5] In conjuction with P3CFGA[5], it configures the functional mode of P35.
4 P3CFGB[4] In conjuction with P3CFGA[4], it configures the functional mode of P34.
3 P3CFGB[3] In conjuction with P3CFGA[3], it configures the functional mode of
P33_INT1.
2 P3CFGB[2] In conjuction with P3CFGA[2], it configures the functional mode of
P32_INT0.
[1]
1 P3CFGB[1] In conjuction with P3CFGA[1], it configures the functional mode of P31.
0 P3CFGB[0] In conjuction with P3CFGA[0], it configures the functional mode of P30.