Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 45 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.2.2.3 P7 register
8.2.2.4 P3CFGA register
[1] When CPU_PD is set to logic 1(see Table 7 on page 16), for P32_INT0 and referring to Section 8.2.1, e_hd
is forced to logic 1.
Remark: When in Hard power down mode, the P35 to P30 pins are forced in quasi
bidirectional mode. Referring to Figure 7
, en_n = e_pu = “1”, e_p = “0”. And e_hd = “1” if
P3x pin value is “1” and e_hd = “0” if P3x pin value is “0”.
Table 64. P7 register (SFR: address F7h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol -----P7[2] P7[1] P7[0]
Reset 11111 1 1 1
Access RRRRR R/W R/W R/W
Table 65. Description of P7 bits
Bit Symbol Description
7 to 3 - Reserved.
2 P7[2] Out of SPI mode: Writing to P7[2] writes the corresponding value to the
P72 pin according to the configuration mode defined by P7CFGA[2] and
P7CFGB[2].
Reading from P7[2] reads the state of P72 pin.
1 P7[1] Out of SPI mode: Writing to P7[1] writes the corresponding value to the
P71 pin according to the configuration mode defined by P7CFGA[1] and
P7CFGB[1].
Reading from P7[1] reads the state of P71 pin.
0 P7[0] Writing to P7[0] writes the corresponding value to the P70_IRQ pin
according to the configuration mode defined by P7CFGA[0] and
P7CFGB[0].
Reading from P7[0] reads the state of P70_IRQ pin.
Table 66. P3CFGA register (SFR: address FCh) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol --P3CFGA[
5]
P3CFGA[
4]
P3CFGA[
3]
P3CFGA[
2]
P3CFGA[
1]
P3CFGA[
0]
Reset 11111111
Access R R R/W R/W R/W R/W R/W R/W
Table 67. Description of P3CFGA bits
Bit Symbol Description
7 to 6 Reserved.
5 P3CFGA[5] In conjuction with P3CFGB[5], it configures the functional mode of P35.
4 P3CFGA[4] In conjuction with P3CFGB[4], it configures the functional mode of P34.
3 P3CFGA[3] In conjuction with P3CFGB[3], it configures the functional mode of P33_INT1.
2 P3CFGA[2] In conjuction with P3CFGB[2], it configures the functional mode of
P32_INT0
[1]
1 P3CFGA[1] In conjuction with P3CFGB[1], it configures the functional mode of P31
0 P3CFGA[0] In conjuction with P3CFGB[0], it configures the functional mode of P30