Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 44 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.2.2 GPIO registers description
8.2.2.1 P7CFGA register
Remark: When in Hard power down mode, the P72 to P70_IRQ pins are forced in quasi
bidirectional mode. Referring to Figure 7
, en_n = e_pu = “1”, e_p = “0”. And e_hd = “1” if
P7x pin value is “1” and e_hd = “0” if P7x pin value is “0”.
8.2.2.2 P7CFGB register
Remark: When in Hard power down mode, the P72 to P70_IRQ pins are forced in quasi
bidirectional mode. Referring to Figure 7
, en_n = e_pu = “1”, e_p = “0”. And e_hd = “1” if
P7x pin value is “1” and e_hd = “0” if P7x pin value is “0”.
Table 60. P7CFGA register (SFR: address F4h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol -----P7CFGA[2]P7CFGA[1]P7CFGA[0]
Reset 11111 1 1 1
Access RRRRR R/W R/W R/W
Table 61. Description of P7CFGA bits
Bit Symbol Description
7 to 3 - Reserved.
2 P7CFGA[2] Out of SPI mode, and in conjuction with P7CFGB[2], it configures the
functional mode of the P72 pin.
1 P7CFGA[1] Out of SPI mode, and in conjuction with P7CFGB[1], it configures the
functional mode of the P71 pin.
0 P7CFGA[0] In conjuction with P7CFGB[0], it configures the functional mode of
P70_IRQ pin.
Table 62. P7CFGB register (SFR: address F5h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol -----P7CFGB[2]P7CFGB[1]P7CFGB[0]
Reset 00000 0 0 0
Access RRRRR R/W R/W R/W
Table 63. Description of P7CFGB bits
Bit Symbol Description
7 to 3 - Reserved.
2 P7CFGB[2] Out of SPI mode, and in conjuction with P7CFGA[2], it configures the
functional mode of the P72 pin.
1 P7CFGB[1] Out of SPI mode, and in conjuction with P7CFGA[1], it configures the
functional mode of the P71 pin.
0 P7CFGB[0] In conjuction with P7CFGA[0], it configures the functional mode of P70_
IRQ pin.