Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 41 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.2.1.2 Quasi Bidirectional
In Quasi Bidirectional configuration, e_p is driven to logic 1 for only one CPU_CLK period
when writing Px[n]. During the t
pushpull
time the pad drives a strong logic 1 at its output.
While zi (GPIO) is logic 1, the weak hold transistor (e_hd) is ON, which implements a latch
function. Because of the weaker nature of this hold transistor, the pad cell can now act as
an input as well.
A third very weak pull-up transistor (e_pu) ensures that an high impedance input is read
as logic 1. e_pu is clocked and is at logic 1 while Px[n] is at logic 1.
On a transition from logic 0 to logic 1 externally driven on GPIO pad, when the voltage on
the pad is at the supply voltage divided by 2, zi goes to logic 1, the pull-up e_hd is ON.
e_hd is an asynchronous signal.
The maximum currents that can be sourced by the e_pu transistor is 80 mA and 500 mA
by e_hd transistor.
Fig 7. Quasi Bidirectional
1
2
Px[n]
zi
e_hd
e_pu
e_p
en_n
GND
DVDD
GND
xVDD
3
Control
PxCFGA[n] = “1”
PxCFGB[n] = “0”
CPU_CLK
en_n
e_hd
output mode
input mode
GPIO pad
Write Px[n]
en_n
zi
e_p
Read Px[n]
GPIO pad
CPU_CLK
CPU_CLK
GPIO pad
e_pu
zi
e_p
e_hd
e_pu
“1”
“1”
“0”
t
pushpull