Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 39 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
where x is 3 or 7 and n is the bit index.
At maximum 4 different controllable modes can be supported. These modes are defined
with the following bits:
• PxCFGA[n]=0 and PxCFGB[n]=0: Open drain
• PxCFGA[n]=1 and PxCFGB[n]=0: Quasi Bidirectional (Reset mode)
• PxCFGA[n]=0 and PxCFGB[n]=1: input (High Impedance)
• PxCFGA[n]=1 and PxCFGB[n]=1: Push/pull output
Px[n] is used to write or read the port value.
Here is the list of the registers used for these GPIO configuration
Table 59. Timer0/1 Special Function registers List
Name Size
[bytes]
SFR address Description Access
P3CFGA 1 FCh Port 3 configuration R/W
P3CFGB 1 FDh Port 3 configuration R/W
P3 1 B0h Port 3 value R/W
P7CFGA 1 F4h Port 7configuration R/W
P7CFGB 1 F5h Port 7 configuration R/W
P7 1 F7h Port 7 value R/W