Datasheet

Table Of Contents
PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 31 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.1.8 Debug UART
The Debug UART is implemented to assist debug using UART_RX and UART_TX pins.
8.1.8.1 Feature list
The Debug UART has the following characteristics:
Full duplex serial port
Receive buffer to allow reception of a second byte while the first byte is being read out
by the CPU
Four modes of operation which support 8-bit and 9-bit data transfer at various baud
rates
Supports multi-processor communication
Baud rate can be controlled through Timer1 or Timer2 baud rate generator
8.1.8.2 Debug UART functional description
The serial port has a receive buffer: a second byte can be stored while the previous one is
read out of the buffer by the CPU. However, if the first byte has still not been read by the
time reception of the second byte is complete, one of the bytes will be lost.
The receive and transmit data registers of the serial port are both accessed by firmware
via the Special Function Register S0BUF. Writing to S0BUF loads the transmit register;
reading from S0BUF accesses a physically separate receive register.
The serial port can operate in 4 modes. These modes are selected by programming bits
SM0 and SM1 in S0CON:
Mode 0:
Serial data are received and transmitted through UART_RX. UART_TX outputs the
shift clock. 8 bits are transmitted/received (LSB first)
Baud rate: fixed at 1/6 of the frequency of the CPU clock
Mode 1:
10 bits are transmitted through UART_TX or received through UART_RX: a start
bit (0), 8 data bits (LSB first), and a stop bit (1)
Receive: The received stop bit is stored into bit RB8 of register S0CON
Baud rate: variable (depends on overflow of Timer1 or Timer2)
Mode 2:
11 bits are transmitted through UART_TX or received through UART_RX: start bit
(0), 8 data bits (LSB first), a 9th data bit, and a stop bit (1)
Transmit: the 9th data bit is taken from bit TB8 of S0CON. For example, the parity
bit could be loaded into TB8.
Receive: the 9th data bit is stored into RB8 of S0CON, while the stop bit is ignored
Baud rate: programmable to either 1/16 or 1/32 the frequency of the CPU clock