Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 27 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.1.6.7 Overflow detection
For both the upper and lower bytes of the Timer0/1, an overflow is detected by comparing
the incremented value of the most significant bit with its previous value. An overflow
occurs when this bit changes from logic 1 to logic 0. An overflow event in the lower byte is
clocked into a flip-flop and is used in the next state as the increment enable for the upper
byte. An overflow event in the upper byte will set the corresponding overflow bit in the
T01CON register to logic 1. The upper byte overflow is also clocked into a flip-flop to
generate the output signals ‘t0_ovf’ and ‘t1_ovf’.
The overflow flags TF0 and TF1, found in register T01CON, are loaded during states S2
and S4 respectively. The interrupt controller of the 80C51 scans all requests at state S2.
Thus, an overflow of Timer0 or Timer1 is detected one machine cycle after it occurred.
When the request is serviced, the interrupt routine sets the overflow flag to logic 0.
Execution of the interrupt routine starts on the fourth machine cycles following the timer
overflow. When Timer0/1 receives the acknowledge from the CPU:
• the overflow flag TF0 in register T01CON is set to logic 0
• two machine cycles later, the overflow flag TF1 in register T01CON is set to logic 0
If during the same machine cycle, an overflow flag is set to logic 0 due to a CPU
acknowledge and set to logic 1 due to an overflow, the set to logic 1 is the strongest.
8.1.7 Timer2 description
Timer2 supports a subset of the standard Timer2 found in the 8052 microcontroller.
Timer2 can be configured into 2 functional modes via the T2CON and T2MOD registers:
• Mode1: Auto-reload up/down counting
• Mode2: Baud rate generation for Debug UART
Timer2 can operate either as a timer or as an event counter.
8.1.7.1 Timer2 registers
Timer2 contains six Special Function Registers (SFRs) which can be accessed by the
CPU.
Timer2 registers can be written to by either hardware or firmware. If both the hardware
and firmware attempt to update the registers T2H, T2L, RCAP2H or RCAP2L during the
same machine cycle, the firmware write takes precedence. A firmware write occurs in
state S6 of the machine cycle.
Table 34. Timer2 SFR register List
Name Size
[bytes]
SFR
address
Description Access
T2CON 1 C8h Timer2 control register R/W
T2MOD 1 C9h Timer2 mode register R/W
RCAP2L 1 CAh Timer2 reload lower byte R/W
RCAP2H 1 CBh Timer2 reload upper byte R/W
T2L 1 CCh Timer2 timer/counter lower byte R/W
T2H 1 CDh Timer2 timer/counter upper byte R/W