Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 26 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.1.6.5 T1L and T1H registers
These are the actual timer/counter bytes for Timer1. T1L is the lower byte, T1H is the
upper byte.
8.1.6.6 Incrementer
The two 16-bit timer/counters are built around an 8-bit incrementer. The Timer0/1 are
incremented in the CPU states S1 to S4; the overflow flags are set in CPU states S2 and
S4.
• CPU state S1: TOL is incremented if Timer0 is set to:
– timer operation
– counter operation and when a 1-to-0 transition is detected on P34 / SIC_CLK input.
• CPU state S2: TOH is incremented if:
– T0L overflows. The overflow flag TF0 in register T01CON is updated.
• CPU state S3: T1L is incremented if Timer1 is set to:
– timer operation or
– counter operation and when a 1-to-0 transition is detected on P35 input.
• CPU state S4: T1H is incremented if:
– T1L overflows. The overflow flag TF1 in register T01CON is updated.
Table 30. Timer0/1 T1L register (SFR address 8Bh), bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol T1L.7 T1L.6 T1L.5 T1L.4 T1L.3 T1L.2 T1L.1 T1L.0
Reset 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 31. Description of T1L bits
Bit Symbol Description
7 to 0 T1L.7 to T1L.0 Timer1 timer/counter lower byte
Table 32. Timer0/1 T1H register (SFR address 8Dh), bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol T1H.7 T1H.6 T1H.5 T1H.4 T1H.3 T1H.2 T1H.1 T1H.0
Reset 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 33. Description of T1H bits
Bit Symbol Description
7 to 0 T1H.7 to T1H.0 Timer1 timer/counter upper byte