Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 25 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.1.6.4 T0L and T0H registers
These are the actual timer/counter bytes for Timer0: T0L is the lower byte; T0H is the
upper byte.
3GATE0Timer0 gate control. Set by firmware only.
When set to logic 1, Timer0 is enabled only when P32_INT0 is high and bit
TR0 of register T01CON is set.
When set to logic 0, Timer0 is enabled.
2C/T0Timer0 timer/counter selector. Set by firmware only.
When set to logic 1, Timer0 is set to counter operation.
When set to logic 0, Timer0 is set to timer operation.
1 to 0 M[01:00] Timer0 mode. Set by firmware only.
• Mode 0: M01 = 0 and M00 = 0
– 8192 timer
– T0L acts as a 5-bit prescaler.
• Mode 1: M01 = 0 and M00 = 1
– 16-bit timer/counter
– T0H and T0L are cascaded.
• Mode 2: M01 = 1 and M00 = 0
– 8-bit auto-reload timer/counter
– T0H stores value to be reloaded into T0L each time T0L overflows.
• Mode 3: M01 = 1 and M00 = 1
– Timer0 split into two 8-bit timer/counters T0H and T0L
– T0H is controlled by the control bit of Timer1: bit TR1 of register
T01CON
– T0L is controlled by standard Timer0 control: “{P32_INT0 OR
(NOT GATE0)} AND bit TR0”.
Table 25. Description of T01MOD bits
…continued
Bit Symbol Description
Table 26. Timer0/1 T0L register (SFR address 8Ah), bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol T0L.7 T0L.6 T0L.5 T0L.4 T0L.3 T0L.2 T0L.1 T0L.0
Reset 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 27. Description of T0L bits
Bit Symbol Description
7:0 T0L.7 to T0L.0 Timer0 timer/counter lower byte
Table 28. Timer0/1 T0H register (SFR address 8Ch), bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol T0H.7 T0H.6 T0H.5 T0H.4 T0H.3 T0H.2 T0H.1 T0H.0
Reset 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 29. Description of T0H bits
Bit Symbol Description
7 to 0 T0H.7 to T0H.0 Timer0 timer/counter upper byte