Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 23 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.1.6.2 T01CON register
The register is used to control Timer0/1 and report its status.
Table 22. Timer0/1 T01CON register (SFR address 88h), bit allocation
Bit 7 6 5 4 3 2 1 0
SymbolTF1TR1TF0TR0 IE1 IT1 IE0 IT0
Reset 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 23. Description of Timer0/1 T01CON register bits
Bit Symbol Description
7TF1 Timer1 overflow.
Set to logic 1 by hardware on a Timer1 overflow. The flag is set to logic 0
by the CPU after 2 machine cycles.
The bit IE0_3 of register IE0 (see Table 11 on page 17
) has to be set to
logic 1 to enable the corresponding CPU interrupt.
6TR1 Timer1 run control. Set by firmware only.
When set to logic 1, Timer1 is enabled.
5TF0 Timer0 overflow.
Set by hardware on a Timer0 overflow. The flag is set to logic 0 by the
CPU after 2 machine cycles.
The bit IE0_1 of register IE0 (see Table 11 on page 17
) has to be set to
logic 1 to enable the corresponding CPU interrupt.
4TR0 Timer0 run control. Set by firmware only.
When set to logic 1, Timer0 is enabled.
3IE1 External Interrupt1 event.
Set to logic 1 by hardware when an external interrupt is detected on
P33_INT1.
The bit IE0_2 of register IE0 (see Table 11 on page 17
) has to be set to
logic 1 to enable the corresponding CPU interrupt.
2IT1 External Interrupt1 control. Set by firmware only.
When set to logic 1, Interrupt1 triggers on a falling edge of P33_INT1.
When set to logic 0, Interrupt1 triggers on a low level of P33_INT1.
1IE0 External Interrupt0 event.
Set to logic 1 by hardware when an external interrupt is detected on
P32_INT0.
The bit IE0_0 of register IE0 (see Table 11 on page 17
) has to be set to
logic 1 to enable the corresponding CPU interrupt.
0IT0 External Interrupt0 control. Set by firmware only.
When set to logic 1, Interrupt0 triggered by a falling edge on P32_INT0.
When set to logic 0, Interrupt0 triggered by a low level on P32_INT0.