Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 22 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
The firmware performs a register read in state S5 and a register write in state S6. The
hardware loads bits TF0 and TF1 of the register T01CON during state S2 and state S4
respectively. The hardware loads bits IE0 and IE1 of the register T01CON during state S1
and reset these bits during state S2. The registers T0L, T0H, T1L, T1H are updated by the
hardware during states S1, S2, S3 and S4 respectively. At the end of a machine cycle, the
firmware load has overridden the hardware load as the firmware writes in state S6.
Table 21. Timer0/1 SFR registers CPU state access
CPU STATE
Register Bit S1 S2 S3 S4 S5 S6
T01CON TF0 HW read SW read SW write
TF1 HW read SW read SW write
IE0 / IE1 HW write HW reset SW read SW write
TOL HW write SW read SW write
TOH HW write SW read SW write
T1L HW write SW read SW write
T1H HW write SW read SW write