Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 211 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
12.25 Timing for the I
2
C interface
[1] The PN532 has a slope control according to the I
2
C specification for the Fast mode. The slope control is
always present and not dependant of the I
2
C speed.
[2] 27.12 MHz quartz starts in less than 800 s. For example, quartz like TAS-3225A, TAS-7 or KSS2F with
appropriate layout.
[3] The PN532 has an internal hold time of around 270ns for the SDA signal to bridge the undefined region of
the falling edge of P50_SCL.
Table 320. I
2
C timing specification
Symbol Parameter Conditions Min Typ Max Unit
f
SCL
SCL clock frequency 0 400 kHz
t
HD; STA
Hold time
(repeated) START condition.
After this period,
the first clock
pulse is generated
600 ns
t
SU; STA
Set-up time
for a repeated START condition
600 ns
t
SU; STO
Set-up time for STOP condition 600 ns
t
LOW
LOW period
of the P50_SCL clock
1300 ns
t
HIGH
HIGH period
of the P50_SCL clock
600 ns
t
HD; DAT
Data hold time 0 900 ns
t
SU; DAT
Data set-up time 100 ns
t
r
Rise time
P50_SCL and SDA
[1]
20 1000 ns
t
f
Fall time
P50_SCL and SDA
[1]
20 300 ns
t
BUF
Bus free time between
a STOP and START condition
1.3 ms
t
StrWuSpd
Stretching time
on P50_SCL
when woken-up
on its own address
[2]
1ms
t
HDSDA
Internal hold time
for SDA
330 590 ns
t
HDSDA
Internal hold time
for SDA in SPD mode
[3]
270 ns
Fig 50. I
2
C timing diagram