Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 203 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
12.14 Input pin characteristics for NSS / P50_SCL / HSU_RX
[1] To minimize power consumption when in Soft-Power-Down mode, the limit is PV
DD
- 0.4 V.
[2] To minimize power consumption when in Soft-Power-Down mode, the limit is 0.4 V.
[3] When PVDD is not present, it is not possible to define a high level on NSS. When using SPI host interface,
a wake-up condition can not be avoided if PVDD is absent.
[1] To minimize power consumption when in Soft-Power-Down mode, the limit is PV
DD
- 0.4 V.
[2] To minimize power consumption when in Soft-Power-Down mode, the limit is 0.4 V.
[3] Data at PVDD= 1.8V are only given from characterization results.
Table 307. Input pin characteristics for NSS / HSU_RX for HSU / SPI interfaces
Symbol Parameter Conditions Min Typ Max Unit
V
IH
High level Input voltage PV
DD
> 1.6V
[1]
[3]
0.7  PV
DD
PV
DD
V
V
IL
Low level Input voltage PV
DD
> 1.6V
[2]
00.3 PV
DD
V
I
IH
High level input current V
I
=DV
DD
-1 1 A
I
IL
Low level input current V
I
=0V -1 1 A
I
Leak
Input leakage current RSTPD_N = 0.4 V -1 1 A
C
in
Input Capacitance 2.5 pF
TSP Width of suppressed
spikes
20 ns
Table 308. Input/open drain output pin characteristics for P50_SCL for I
2
C interface
Symbol Parameter Conditions Min Typ Max Unit
V
IH
High level Input voltage
[1]
0.7  PV
DD
PV
DD
V
V
IL
Low level Input voltage
[2]
00.3 PV
DD
V
V
OL
Low level output voltage PV
DD
=3V,
I
OL
=4mA
00.3V
PV
DD
=1.8V,
I
OL
=2mA
[3]
00.3V
I
IH
High level input current V
I
=DV
DD
-1 1 A
I
IL
Low level input current V
I
=0V -1 1 A
I
Leak
Input leakage current RSTPD_N = 0.4 V -1 1 A
C
in
Input Capacitance 2.5 pF
C
out
Load Capacitance 30 pF
T
SP
Width of suppressed
spikes
Out of SPD mode 20 ns
T
SP
Width of suppressed
spikes
In SPD mode 120 ns