Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 20 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.1.5.4 General purpose IRQ control
The general purpose interrupts are controlled by register GPIRQ.
NOTE: this is not a standard feature of the 8051.
[1] The bit IE1_7 of register IE1 (see Table 13 on page 18) has also to be set to logic 1 to enable the
corresponding CPU interrupt.
Table 18. GPIRQ register (address 6107h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol gpirq_
level_
P71
gpirq_
level_
P50
gpirq_
level_
P35
gpirq_
level_
P34
gpirq_
enable
_P71
gpirq_
enable_
P50
gpirq_
enable_
P35
gpirq_
enable_
P34
Reset 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 19. Description of GPIRQ bits
Bit Symbol Description
7 gpirq_level_P71 Configures the polarity of signal on P71 to generate a GPIRQ
interrupt event (assuming gpirq_enable_P71 is set).
When set to logic 0, an interrupt will be generated if P71 is at logic 0.
When set to logic 1, an interrupt will be generated if P71 is at logic 1.
6 gpirq_level_P50 Configures the polarity of signal on P50 to generate a GPIRQ
interrupt event (assuming gpirq_enable_P50 is set).
When set to logic 0, an interrupt will be generated if P50_SCL is at logic 0.
When set to logic 1, an interrupt will be generated if P50_SCL is at logic 1.
5 gpirq_level_P35 Configures the polarity of signal on P35 to generate a GPIRQ
interrupt event (assuming gpirq_enable_P35 is set).
When set to logic 0, an interrupt will be generated if P35 is at logic 0.
When set to logic 1, an interrupt will be generated if P35 is at logic 1.
4 gpirq_level_P34 Configures the polarity of signal on P34 to generate a GPIRQ
interrupt event (assuming gpirq_enable_P34 is set).
When set to logic 0, an interrupt will be generated if P34 is at logic 0.
When set to logic 1, an interrupt will be generated if P34 is at logic 1.
Remark: If hide_svdd_sig of the register control_rngpower is set and
gpirq_enable_P34 is also set then this bit will be asserted independently
of the level on the pad P34.
3 gpirq_enable_P71 When set to logic 1, enables pad P71 to generate a GPIRQ interrupt
event.
[1]
2 gpirq_enable_P50 When set to logic 1, enables pad P50_SCL to generate a GPIRQ interrupt
event.
[1]
1 gpirq_enable_P35 When set to logic 1, enables pad P35 to generate a GPIRQ interrupt
event.
[1]
0 gpirq_enable_P34 When set to logic 1, enables pad P34 to generate a GPIRQ interrupt
event.
[1]