Datasheet

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PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved. Product data sheet COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 193 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
[1] This register is not described in this document as it is a standard 80C51 register.
D4h CIU_CommIrq Set1 TxIRq RxIRq IdleIrq HiAltertIRq LoAlertIRq ErrIRq TimerIRq
D5h CIU_DivIrq Set2 Reserved SiginActIrq ModeIRq CRCIRq RfOnIRq RfOffIRq
D6h CIU_Error WrErr TempErr RFErr BufferOvfl CollErr CRCErr ParityErr ProtocollErr
D7h Reserved
D8h I
2
CCON CR[2] ENS1 STA STO SI AA CR[1:0]
D9h I
2
CSTA ST[7:0]
DAh I
2
CDAT I
2
CDAT[7:0]
DBh I
2
CADR SA[6:0] GC
DCh to DEh Reserved
DFh CIU_Status1 CIU_IRQ_1 CRCOk CRCReady CIU_IRQ_0 TRunning RFOn HiAlert LoAlert
E0h
[1]
ACC Accumulator ACC[7:0]
E1h to E7h Reserved
E8h IE1 IE1_7 Reserved IE1_5 IE1_4 IE1_3 IE1_2 Reserved IE1_0
E9h CIU_Status2 TempSensClear Reserved RFFreqOK TgActivated MFCrypto1On ModemState[2:0]
EAh CIU_FIFOData FIFOData[7:0]
EBh CIU_FIFOLevel FlushBuffer FIFOLevel[6:0]
ECh CIU_WaterLevel WaterLevel[5:0]
EDh CIU_Control TStopNow TStartNow WrNFCIP-1ID to
FIFO
Initiator Reserved RxLastBits[2:0]
EEh CIU_BitFraming StartSend RxAlign[2:0] Reserved TxLastBits[2:0]
EFh CIU_Coll ValuesAfterColl CollPosNotValid CollPos
F0h
[1]
B register B[7:0]
F1h to F3h Reserved
F4h P7FGA P7CFGA[2] P7CFGA[1] P7CFGA[0]
F5h P7FGB P7CFGB[2] P7CFGB[1] P7CFGB[0]
F6h Reserved
F7h P7 P7[2] P7[1] P7[0]
F8h IP1 IP1_7 IP1_5 IP1_4 IP1_3 IP1_2
F9h Reserved
FAh
[1]
XRAMP XRAMP[4:0]
FBh Reserved
FCh P3FGA P3CFGA[5] P3CFGA[4] P3CFGA[3] P3CFGA[2] P3CFGA[1] P3CFGA[0]
FDh P3FGB P3CFGB[5] P3CFGB[4] P3CFGB[3] P3CFGB[2] P3CFGB[1] P3CFGB[0]
FEh to FFh Reserved
Table 289. SFR registers mapping …continued
SFR
address
Register name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0