Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 19 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
The 2 following tables describe IP0.
The 2 following tables describe IP1.
Table 14. Interrupt controller IP0 register (SFR: address B8h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol IP0_7 IP0_6 IP0_5 IP0_4 IP0_3 IP0_2 IP0_1 IP0_0
Reset 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 15. Description of IP0 bits
Bit Symbol Description
7 IP0_7 Reserved
6 IP0_6 When set to logic 1, NFC-WI interrupt is set to high priority.
5 IP0_5 When set to logic 1, Timer2 interrupt is set to high priority.
4 IP0_4 When set to logic 1, Debug UART interrupt is set to high priority.
3 IP0_3 When set to logic 1, Timer1 interrupt is set to high priority.
2 IP0_2 When set to logic 1, external P33_INT1 pin is set to high priority.
1 IP0_1 When set to logic 1, Timer0 interrupt is set to high priority.
0 IP0_0 When set to logic 1, external P32_INT0 pin is set to high priority.
Table 16. Interrupt controller IP1 register (SFR: address F8h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol IP1_7 - IP1_5 IP1_4 IP1_3 IP1_2 -
Reset 000000 00
Access R/W R/W R/W R/W R/W R/W R/W
Table 17. Description of IP1 bits
Bit Symbol Description
7 IP1_7 When set to logic 1, General Purpose IRQ interrupt is set to high priority.
6- Reserved. This bit must be set to logic 0.
5 IP1_5 When set to logic 1, combined SPI, FIFO and HSU interrupt is set to high
priority.
4 IP1_4 When set to logic 1, I
2
C interrupt is set to high priority.
3 IP1_3 When set to logic 1, CIU interrupt 0 is set to high priority.
2 IP1_2 When set to logic 1, CIU interrupt 1 is set to high priority.
1- Reserved. This bit must be set to logic 0.
0 IP1_0 When set to logic 1, interrupt number 7 is set to high priority.