Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 183 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.6.23.49 CIU_TestPinValue register (6324h)
Defines the values for the 7 bit test bus signals to be I/O on P70_IRQ, RSTOUT_N, P35,
P34 / SIC_CLK, P33_INT1, P32_INT0, P31 / UART_TX and P30 / UART_RX pins.
8.6.23.50 CIU_TestBus register (6325h)
Shows the status of the internal test bus.
Table 270. CIU_TestPinValue register (address 6324h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol useio TestPinValue[6:0]
Reset 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 271. Description of CIU_TestPinValue bits
Bit Symbol Description
7 useio Set to logic 1, this bit enables the I/O functionality for the internal test
bus on the pins P70_IRQ (MSB), RSTOUT, P35, P34 / SIC_CLK,
P33_INT1, P32_INT0, P31 / UART_TX, P30 / UART_RX (LSB)
Note: Before using P34 / SIC_CLK as a test output, the SVDD switch
should be closed. See register address 6106h.
6 to 0 TestPinValue[6:0] UseIO set to logic 1, Read or write the value of the test bus.
UseIO set to logic 0, Read 000_0000. No write.
Table 272. CIU_TestBus register (address 6325h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol TestBus[7:0]
Reset xxxxxxxx
Access RRRRRRRR
Table 273. Description of CIU_TestBus bits
Bit Symbol Description
7 to 0 TestBus[7:0] Shows the status of the internal test bus. The test bus is selected by the
register CIU_TestSel2.
See Section 8.6.21.2 “
CIU test bus” on page 141.