Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 18 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
The 2 following tables describe IE1.
8.1.5.3 Interrupt prioritization: IP0 and IP1 registers
Each interrupt source can be individually programmed to be one of two priority levels by
setting or clearing a bit in the interrupt priority registers IP0 and IP1. If two interrupt
requests of different priority levels are received simultaneously, the request with the high
priority is serviced first. On the other hand, if the interrupts are of the same priority,
precedence is resolved by comparing their respective conflict resolution levels (see
Table 9 on page 16
for details). The processing of a low priority interrupt can be
interrupted by one with a high priority.
A RETI (Return From Interrupt) instruction jumps to the address immediately succeeding
the point at which the interrupt was serviced. The instruction found at the return address
will be executed, prior to servicing any pending interrupts.
Table 12. Interrupt controller IE1 register (SFR: address E8h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol IE1_7 - IE1_5 IE1_4 IE1_3 IE1_2 - IE1_0
Reset 0 0 000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 13. Description of IE1 bits
Bit Symbol Description
7 IE1_7 General purpose IRQ interrupt enable.
When set to logic 1, enables interrupt function of P34, P35, P50_SCL and P71
according to their respective enable and level control bits. See Table 19 on
page 20, Table 137 on page 95 and Table 143 on page 97.
6 - Reserved. This bit must be set to logic 0
5 IE1_5 FIFO, SPI and HSU interrupt enable.
When set to logic 1, enables FIFO interrupts, SPI interrupts, HSU interrupt.
In HSU mode, the interrupt is when NSS is at logic 0.
For the FIFO interrupts, see Table 112 on page 76
.
For the SPI interrupts, see Table 122 on page 81.
4 IE1_4 I2C interrupt enable.
When set to logic 1, enables I
2
C interrupt. See Table 77 on page 54.
3 IE1_3 CIU interrupt 0 enable.
When set to logic 1, enables CIU interrupt 0: CIU_IRQ_0. See Table 190 on
page 151.
2 IE1_2 CIU interrupt 1 enable.
When set to logic 1, enables the CIU interrupt 1: CIU_IRQ_1. See Table 190
on page 151.
1 - Reserved. This bit must be set to logic 0.
0 IE1_0 LDO overcurrent interrupt enable.
When set to logic 1, enables the LDO overcurrent detection interrupt. See
Table 127 on page 88
.