Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 179 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.6.23.41 CIU_TPrescaler register (631Bh)
Define the LSB of the Timer-Prescaler.
8.6.23.42 CIU_TReload_hi register (631Ch)
Defines the MSB of the 16-bit long timer reload value.
Table 254. CIU_TPrescaler register (address 631Bh) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol TPrescaler_LO[7:0]
Reset 000 0 0000
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 255. Description of CIU_TPrescaler bits
Bit Symbol Description
7 to 0 TPrescaler_LO[7:0] Defines lower 8 bits for TPrescaler.
The following formula is used to calculate f
Timer
For detailed description see Section 8.6.17 “
CIU_timer” on page
130.
Note: The TPreScaler time is defined with TPreScaler_Hi[3:0] in
CIU_TMode and TPreScaler_LO[7:0] in this register.
f
Timer
6,78MHz T
PreSca ler
=
Table 256. CIU_TReloadVal_hi register (address 631Ch) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol TReloadVal_Hi[7:0]
Reset 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 257. Description of CIU_TReloadVal_hi bits
Bit Symbol Description
7 to 0 TReloadVal_Hi[7:0] Defines the higher 8 bits for the TReloadValue.
With a start event the timer loads with the TReloadValue. Changing
this register affects the timer only with the next start event.
Note: The reload value is defined with TReloadVal_Hi[7:0] in this
register and TReloadVal_Lo[7:0] in CIU_TReloadVal_lo